signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 website: http://www.spt.com e-mail: sales@spt.com SPT104 dc to 1.1ghz linear amplifier features ? C3db bandwidth of 1.1 ghz ? 325psec rise and fall times ? 14db gain, 50 w input and output ? low distortion, linear phase ? 1.4:1 vswr (output, dc-1.1 ghz) ? direct replacement for clc104 applications ? digital and wideband analog communications ? radar, if and rf processors ? fiber optic drivers and receivers ? photomultiplier preamplifiers equivalent circuit diagram basic circuit diagram general description the SPT104 linear amplifier represents a significant ad- vance in linear amplifiers. proprietary design techniques have yielded an amplifier with 14db of gain and a C3db bandwidth of dc to 1100mhz. gain flatness to 750mhz of 0.4db coupled with excellent vswr and phase linearity gives outstanding pulse fidelity and low signal distortion. designed for 50 w systems, the SPT104 is very easy to use, requiring only properly bypassed power supplies for opera- tion. this translates to time and cost savings in all stages of design and production. fast rise time, low overshoot and linear phase make the SPT104 ideal for high-speed pulse amplification. these properties plus low distortion combine to produce an ampli- fier well suited to many communications applications. with a 1.1ghz bandwidth, the SPT104 can handle the fastest digi- tal traffic, even when the demodulation scheme or the digital coding format requires that dc be maintained. it is also ideal for traditional video amplifier applications such as radar or wideband analog communications systems. these same characteristics make the SPT104 an excellent choice for use in fiber optics systems, on either the transmit- ting or receiving end of the fiber. the low group delay distor- tion insures that pulse integrity will be maintained. as a pho- tomultiplier tube pre-amp, its fast response and quick overload recovery provide for superior system performance. the SPT104 is constructed using thin film resistor/bipolar transistor technology, and is available in the following ver- sions: SPT104ai C25 c to +85 c 14-pin double-wide dip
spt 2 9/30/99 SPT104 parameters conditions typ min & max ratings units sym ambient temperature +25 c min max frequency domain response ? -3db bandwidth 0dbm out 1100 1000 mhz ssbw 10dbm out 1050 mhz ssbw ? non-inverting gain (note 1) @ 100mhz 14.2 13.8 14.9 db ? gain flatness dc - 750mhz 0.4 -0.6 +0.6 db linear phase deviation dc - 600mhz 1.5 3 lpd group delay 600 ps gd reverse isolation dc - 750mhz 40 db rini 750mhz - 1100mhz 35 db riin input return loss dc - 750mhz 18 db 750mhz - 1100mhz 11 db output return loss dc - 750mhz 17 db 750mhz - 1100mhz 10 db time domain response rise and fall time 1v step 325 375 ps trs (10% to 90%) 2v step 375 450 ps trl settling time to 0.8% 1v step 1.2 ns ts overshoot 1v step 3 % os overload recovery v inpeak = 0.5v 1.2 1.6 ns or noise and distortion response ? 2nd harmonic distortion 0dbm, 100mhz 47 -dbc hd2 ? 3rd harmonic distortion 0dbm, 100mhz 53 -dbc hd3 ? 2nd harmonic distortion 10dbm, 100mhz 40 30 -dbc hd2 ? 3rd harmonic distortion 10dbm, 100mhz 43 35 -dbc hd3 3rd order intermodulation intercept 100mhz 26 +dbm 2-tone, 1mhz separation 500mhz 17 equivalent input noise voltage 10hz to 1200mhz 55 db noise figure 11 db usable dynamic range 100mhz 71 db 500mhz 65 db static, dc performance input bias current note 2 80 280 m a ibn input bias current (drift) note 2 0.6 2.0 m a/ c ibn output offset voltage note 3 50 250 mv output offset voltage (drift) note 3 375 625 m v/ c * supply current no load 54 60 ma icc supply rejection ratio 1khz 55 db psrr min/max ratings are based on product characterization and simulation. individual parameters are tested as noted. outgoing quali ty levels are determined from tested parameters. SPT104 electrical characteristics (t a = +25 c, v cc = 15v, r l = 50 w , r s = 50 w ; unless specified) absolute maximum ratings v cc 9v to 16v i o 40ma input voltage 0.5v junction temperature +175 c operating temperature ai: -25 c to +85 c storage temperature -65 c to +150 c notes 1. nominal gain only - gain variation over temperature is 0.1db. 2. input offset voltage = (input bias current) x (r s || 50 w ). 3. output offset can be adjusted to zero with an external potenti- ometer C see reducing dc offset. 4. * ai 100% tested at 25 c. ? ai sample tested at 25 c.
spt 3 9/30/99 SPT104 typical performance characteristics (t a = +25 c, v cc = 15v, r l = 50 w , r s = 50 w ; unless specified)
spt 4 9/30/99 SPT104 pc board layout considerations proper layout of printed circuit boards is important to achieve optimum performance of a circuit operating in the 1ghz frequency range. use of microstripline is recom- mended for all signal-carrying paths and low resistance, low inductance signal return and bypass paths should be used. to keep the impedance of these paths low, use as much ground plane as possible. ground plane also serves to in- crease the flow of heat out of the package. the SPT104 has three types of connections: signal paths (input and output), dc inputs (supplies and offset adjust), and grounds. 50 w microstrip is recommended for connec- tion to the input (pin 4) and output (pin 11). microstrip on a doublesided pc board consists of a ground plane on one side of the board and a constant-width signal-carrying trace on the other side of the board. for 1/16" g10 or fr-4 pc board material, a 0.1" wide trace will have a 50 w character- istic impedance. the ground plane beneath the signal trace must extend at least one trace width on either side of the trace. also, all traces (including ground) should be kept at least one trace width from the signal-carrying traces. to keep power supply noise and oscillations from appear- ing at the amplifier output, all supply pins should be capaci- tively bypassed to ground. the power supply pins (1 and 2) are the inputs to a pair of voltage regulators whose outputs are at pins 13 and 14. it is recommended that 0.01 m f or larger ceramic capacitors be connected from pins 1, 2, 13 and 14 to ground, within 0.2" of the pins. a 1 m f or larger solid tantalum capacitor to ground is required within 3" of pins 1 and 2, and for good low frequency performance, solid tantalum capacitors of at least 15 m f should be connected from pins 13 and 14 to ground within 3" of the pins. use 0.025" or wider traces for the supply lines. the offset adjust pin (12) also requires bypassing; a 0.01 m f or larger ceramic capacitor to ground within 0.2" of the pin is recommended. grounding is the final layout consideration. pins 3 and 5-10 should all be connected to a ground plane which should cover as much of one side of the board around the amplifier as possible. reducing dc offset dc offset of the SPT104 may be adjusted by applying a dc voltage to the amplifiers offset adjust pin (12). the simplest method is shown in figure 1. using this method of offset adjust it is possible to vary the output offset by approxi- mately 400mv. this simple adjustment has no effect on the offset drift characteristics of the SPT104. figure 1: basic circuit if lower offset and offset drift are required, a low frequency op amp may be used in conjunction with the SPT104 in a composite configuration. the suggested circuit appears in figure 2. its method of operation is to compare an attenu- ated version of the output signal to the input signal and ap- ply a correcting voltage at the offset adjust pin. a compensa- tion capacitor c s reduces the bandwidth of the op amp correction circuit to limit the op amps effect on the SPT104 to frequencies below f 45 , the frequency at which the op amp has 45db of open loop gain. using an lm108, f 45 is about 7hz with c s = 0.1 m f. thus the op amp can correct dc and low frequency errors below f 45 , without affecting SPT104 performance above f 45 . also note that the noise perfor- mance of the op amp will dominate below f 45 . figure 2: composite amplifier with an lm108 op amp in this composite configuration, in- put offset is typically 2mv and drift is 15mv/ c. at frequen- cies well below f 45 , the composite gain is equal to (1 + 49.9k/(r a + r b )) and the output impedance is very low. as
spt 5 9/30/99 SPT104 the signal frequency increases beyond f 45 , the op amp loses influence and the SPT104 gain and output impedance domi- nate. to ensure a smooth transition and matched gain at all frequencies, adjust r b for a minimum op amp output swing with a 0.1v pp sinewave input (to the SPT104) at the fre- quency f 45 . since the SPT104 has a 50 w output impedance, its output voltage is a function of the load impedance (a v ~ 10r l /(r l + 50)), whereas the gain of the composite amplifier at low frequencies and dc is relatively indepen- dent of the load impedance, due to the high open-loop gain of the op amp. thus, to avoid gain mismatching and phase non-linearity, use the composite amplifier only if the load impedance is constant from dc to at least 10(f 45 ). use of a composite amplifier reduces input offset voltage and its corresponding drift, but has no effect on input bias current. this current is converted to an input voltage by the resistance to ground seen at the amplifier input and the volt- age appears, amplified, at the output. typical input offset voltage due to the bias current is 2mv and input offset drift is approximately 15mv/ c. thermal considerations the SPT104 case must be maintained at or below 140 c. note that because of the amplifier design, power dissipation remains fairly constant, independent of the load or drive level. therefore, standard derating is not possible. there are two ways to keep the case temperature low. the first is to keep the amount of power dissipated inside the package to a minimum and the second is to get the heat out of the package quickly by reducing the thermal resistance from case to ambient. a large portion of the heat dissipated inside the package is in the voltage regulators. at the minimum +9v supply level the regulators dissipate 390mw and at the maximum 16v supply level they dissipate 1.2w. the amplifier itself dissipates a fairly constant 600mw (55ma x 10.8v). reducing the power dissipation of the in- ternal regulators will go far towards reducing the internal junction temperatures without impacting the performance. reducing either the input supply voltages (on pins 1 and 2) and/or shunting the regulator current through external resis- tors (from pins 1 to 14 and pins 2 to 13) are both effective means towards significantly reducing the internal power dis- sipation. a minimum voltage across the regulator of 3.6v and a minimum regulator current of 10ma will satisfy the regulator dropout voltage and current limits. given the maximum anticipated power supply voltages, the shunt resistor should be calculated to yield a 35ma current from that voltage to the regulated voltage of 5.4v. this will leave 10ma through the regulator at the minimum quiescent current of 45ma. the regulator input voltages may be re- duced directly by dropping the voltage supplies, or, if that option is not available, using either a zener or resistive drop- ping element in series with the supply. if a series dropping element is used, the decoupling capacitors must appear on pins 1 and 2 of the SPT104. figure 3 shows two possible power reduction circuits from fixed 15v supplies. several methods of decreasing the thermal resistance from case to ambient are possible. with no heat paths other than still air at 25 c, the thermal resistance from case to ambient for the SPT104 is about 40 c/w. when placed in a printed circuit board with all ground pins soldered into a ground plane 1" x 1.5", the thermal resistance drops to about 30 c/w. in this configuration, the case rise will be 30 c for 9v supplies and 50 c for 16v supplies. this results in maxi- mum allowable ambient temperatures of 110 c and 90 c, respectively. if higher operating temperatures are required, heat sinking of the package is recommended. figure 3: reducing power dissipation package dimensions
spt 6 9/30/99 SPT104 signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited . warning C life support applications policy C spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, ca n be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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